1. Field of the Invention
This application is directed to three-dimensional interconnect structures and methods for advanced integrated circuit fabrication.
2. Description of the Related Art
Three-dimensional (3D) integration is an emerging market in which several technology approaches are currently under development or implementation. In the fabrication of electrical interconnects for 3D integration, there are many variables which determine the specific process methods which can be used to make an interconnect of suitably low resistance. A variety of suitable methods have been established for making the interconnect levels required for IC fabrication, including recent copper interconnect technologies. However, for the fabrication of 3D interconnects (such as those going through silicon substrates) the process methods are still being developed by a variety of research groups, and currently there are no industry-standard approaches. Further, the fabrication of 3D interconnects introduces several technical challenges beyond those normally associated with making traditional IC internal interconnects.
Three dimensionally-integrated circuits with multiple interconnected levels have shorter vertical interconnects as opposed to long horizontal lines and therefore benefit from shorter signal propagation delays, lower power consumption and reduced crosstalk noise. Also, the vertical integration of different types of devices (microprocessor, memory, analog, RF, MEMS, optical) in the same 3D structure significantly reduces overall package size.
Some variables which relate to specific designs and applications of the 3D interconnects include: via size and aspect ratio, type of metal pad to be contacted (usually the metal on the underlying substrate, which the 3D via in the top substrate will connect to), and type of metal to be used in forming the 3D interconnect. Further, there are different approaches for the 3D integration which impact the processes used. These approaches may be referred to as “vias-first” or “vias-last.” For instance, in the “vias first” approach, vias may be etched into a device substrate to a desired depth, then coated with a dielectric and filled with a via metal prior to thinning of the device substrate and bonding to an underlying base substrate for 3D integration. In such an approach, a metal-to-metal bonding method (such as solder bonding, diffusion bonding, eutectic bonding, or thermocompression bonding) is generally used to achieve both mechanical joining and electrical interconnection of the substrates. In the “vias last” approach, a device substrate is bonded to a base substrate. Deep vias are bored through the device substrate until metal pads on the base substrate are reached. The exposed metal pads and the bored vias have a via-metal deposited thereon and therein, respectively, to form a conducting electrical interconnect between the base substrate and the device substrate. In the vias-last approach, the via etch may have to pass through more than just the substrate layer, but also any bonding layer or additional insulator layers present between the substrates. It may also be necessary to etch a deposited via dielectric selectively from the surface of the exposed metal pads. Further, the surface of the metal pad on the underlying substrate will be exposed to the etch processes used to remove these layers. In the process, this surface can become oxidized, chemically modified, or otherwise contaminated and must be properly cleaned or treated prior to depositing the via metal to form a 3D interconnect of suitably low resistance and high reliability.
In many microelectronic substrate interconnect schemes, tungsten is typically used on a top or bottom of any metallic pads, providing more flexibility in the design space. Conventionally, the problem of providing a suitable electrical contact resistance between tungsten and copper vias have been resolved by high temperatures. However, the need to anneal the substrate to form a low contact resistance contact between the metal pad material and the 3D via metal has limited the vias last technology.